Job description
Job details
- Location: US
- Work mode: Remote
- Employment type: Full-time (Not an internship)
- Salary: USD 131,762 per year
Role overview
TechSpace Solutions Inc. is looking for a Lead ASIC DFT Engineer to drive Design-for-Test strategies for complex integrated circuits. This is a high-impact role requiring a deep understanding of scan architectures and pattern generation to ensure hardware reliability and testability.
Job details
This is a full-time, Remote position based in the US, requiring alignment with the PST time zone. This role is not an internship. The offered salary for this position is 131,762 USD.
Responsibilities
- Lead the development and implementation of ASIC Design-for-Test (DFT) architectures.
- Execute ATPG, MBIST, and scan chain insertions to optimize test coverage.
- Perform timing simulations using SDF and SDC to validate test patterns.
- Manage pattern retargeting and porting processes across different platforms.
- Conduct detailed diagnosis and resolve DRC violations to ensure tape-out readiness.
- Collaborate with design teams to integrate DFT features into the RTL flow.
Requirements
- Over 10 years of hands-on experience in ASIC Design-for-Test (DFT) engineering.
- Expertise with industry-standard tools such as TetraMax and DFTMax.
- Proven experience with SCAN, ATPG, MBIST, and PSV methodologies.
- Strong proficiency in timing simulations, SDF, and SDC constraints.
- Demonstrated ability to handle pattern porting and complex diagnosis tasks.
- Ability to work remotely while maintaining alignment with PST time zone.
Benefits
- Competitive salary package
- Fully remote work flexibility
- Opportunity to lead high-complexity ASIC projects
- Long-term career stability
Keywords
ASICDFTATPGMBISTTetraMaxDFTMaxSDCSDFScan ChainPattern Retargeting