Job description
Job details
- Location: Campbell, Santa Clara County
- Work mode: Remote
- Employment type: Full-time (Not an internship)
- Salary: USD 113,357 per year
Role overview
Tanisha Systems is seeking a seasoned Lead ASIC DFT Engineer to drive the architecture and implementation of Design-for-Test strategies. This high-impact role focuses on ensuring the reliability and testability of complex ASIC designs through advanced verification and debugging techniques.
Job details
This is a full-time, remote position based in Campbell, Santa Clara County, requiring alignment with the PST time zone. This is not an internship. The offered salary for this position is 113,357 USD.
Responsibilities
- Architect and implement comprehensive Design-for-Test (DFT) strategies for complex ASIC designs.
- Lead the verification and debugging process to ensure high test coverage and hardware reliability.
- Collaborate with cross-functional design teams to integrate DFT structures into the RTL.
- Develop and optimize ATPG patterns to reduce test time and improve fault coverage.
- Provide technical leadership and mentorship to junior engineers on the hardware team.
Requirements
- Minimum of 15 years of hands-on experience in ASIC Design-for-Test (DFT).
- Proven track record of leading DFT architecture from specification to tape-out.
- Expertise in scan compression, MBIST, and boundary scan standards.
- Strong proficiency in hardware description languages and industry-standard DFT tools.
- Ability to work remotely while remaining fully aligned with the PST time zone.
Benefits
- Fully remote work flexibility
- Competitive annual salary
- Opportunity to lead high-priority hardware projects
- Professional growth in a specialized technical domain
Keywords
ASICDFTDesign-for-TestVerificationHardware ArchitectureDebuggingVLSIPST Timezone