Key Responsibilities • Create and optimize floorplans for analog and mixed-signal blocks in advanced 7nm FinFET technology. • Translate sub-block schematics into physical layouts while maintaining hierarchy and design intent. • Perform detailed transistor-level and block-level layout implementation for high-speed circuits. • Ensure layout matches parameterized devices (PCells) and simulation hierarchy on a one-to-one basis. • Follow design documentation, review comments, customer feedback, and …