Job description
Job details
- Location: US
- Work mode: Remote
- Employment type: Contract (Not an internship)
- Salary: USD 122,572 per year
Role overview
VDart, Inc. is seeking a Lead ASIC DFT Engineer to drive the architecture and implementation of advanced Design-for-Test solutions for complex ASIC and SoC designs. This is a high-impact role requiring deep technical ownership of the DFT lifecycle, from initial architecture to final verification and debug, ensuring high test coverage and silicon quality.
Job details
This is a contract position based in the US, offering a fully Remote work mode, provided the candidate is aligned with the PST time zone. This is not an internship. The offered salary for this role is 122,572 USD.
Responsibilities
- Architect and implement advanced DFT solutions for complex ASIC and SoC designs.
- Lead the execution of scan insertion, ATPG, and boundary scan strategies.
- Develop and verify MBIST and LBIST implementations to ensure high fault coverage.
- Perform deep-dive debugging of DFT-related issues during the design and verification phases.
- Collaborate with design and verification teams to optimize testability and reduce test time.
- Provide technical leadership and ownership across the entire DFT flow.
Requirements
- Minimum of 10 years of hands-on experience in ASIC Design-for-Test (DFT).
- Proven expertise in scan insertion, ATPG, and JTAG standards.
- Deep technical knowledge of MBIST and LBIST architectures for SoC designs.
- Strong experience with industry-standard DFT tools and methodologies.
- Ability to work remotely while maintaining alignment with the PST time zone.
- Excellent problem-solving skills for debugging complex hardware test issues.
Benefits
- Fully remote work flexibility
- Opportunity to work on cutting-edge SoC designs
- Competitive contract compensation
- Professional growth in a lead technical capacity
Keywords
ASICDFTATPGMBISTLBISTJTAGSoCBoundary ScanScan InsertionHardware Verification