Job description
Job details
- Location: California, US
- Work mode: Remote
- Employment type: Full-time (Not an internship)
- Salary: USD 170,757 per year
Role overview
Innovim Technology Solutions is seeking a Lead ASIC DFT Engineer to drive design-for-test strategies for complex integrated circuits. This is a high-seniority position requiring extensive expertise in scan, ATPG, and timing simulations to ensure hardware reliability and testability.
Job details
This is a full-time, remote position based in California, US, requiring alignment with the PST time zone. This is not an internship. The offered salary for this role is 170,757 USD.
Responsibilities
- Lead the ASIC Design-for-Test (DFT) architecture and implementation process.
- Develop and execute SCAN, ATPG, and MBIST strategies for complex chips.
- Perform timing simulations using SDF and SDC to ensure signal integrity.
- Manage pattern retargeting and pattern porting across different test platforms.
- Conduct detailed diagnosis and resolve DRCs to optimize test coverage.
- Utilize TetraMax and DFTMax tools to implement high-quality test patterns.
Requirements
- Minimum of 10 years of hands-on experience in ASIC Design-for-Test (DFT).
- Expertise in SCAN, ATPG, and MBIST methodologies.
- Proficiency with industry-standard tools including TetraMax and DFTMax.
- Strong understanding of Timing Simulations, SDF, and SDC constraints.
- Proven track record in pattern retargeting and hardware diagnostics.
- Ability to work remotely while remaining aligned with the PST time zone.
Benefits
- Competitive annual salary of 170,757 USD.
- Fully remote work environment.
- Opportunity to lead high-impact ASIC projects.
- Professional growth in a specialized technical field.
Keywords
ASICDFTATPGMBISTTetraMaxDFTMaxScanSDFSDCTiming Simulations